High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator

Mersenne Twister uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical tablebased architecture, a new architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures have been proven in a high performance Gaussian RNG.